1. Field of the Invention
The present invention relates to a scan driving circuit and to a display device including the scan driving circuit. More particularly, the present invention relates to a scan driving circuit and to a display device including the scan driving circuit, in which signals can be supplied to scanning lines, initialization control lines, and display control lines, and a lit/unlit state of display elements can be switched multiple times during one field period by supplying multiple pulse signals to the display control lines during the field period, without affecting the signals being supplied to the scanning lines and initialization control lines.
2. Description of the Related Art
Examples of widely used display devices having display elements arranged in the form of a two-dimensional matrix include liquid crystal display devices made up of liquid crystal cells driven by voltage, and also display devices including light emitting units which emit light under application of electric current (e.g., organic electroluminescence light emitting units) and driving circuits for driving the light emitting units.
The luminance of display elements including light emitting units which emit light under application of electric current is controlled by the value of the current flowing through the light emitting units. In the same way as with liquid crystal display devices, such display devices having these display elements (e.g., organic electroluminescence display devices) can be driven by the simple matrix method and the active matrix method. While the active matrix method has shortcomings such as greater complexity in structure as compared with the simple matrix method, there are also various advantages, such as being capable of higher luminance.
Various types of driving circuits configured from transistors and capacitance units are in widespread use as circuits for driving a light emitting unit by the active matrix method. For example, Japanese Unexamined Patent Application Publication No. 2005-31630 discloses a display element configured of an organic electroluminescence light emitting unit and a driving circuit, and a driving method thereof. This driving circuit is a driving circuit configured of six transistors and one capacitance unit (hereinafter referred to as “6Tr/1C driving circuit”). FIG. 26 illustrates an equivalent circuit to a driving circuit (6Tr/1C driving circuit) of a display element of the m′th row and n′th column in a display device configured of display elements arrayed in the form of a two-dimensional matrix. Note that in the description, the display elements are assumed to be scanned in line sequence.
The 6Tr/1C driving circuit has a write transistor TRW, a driving transistor TRD, a capacitance unit C1, and also a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4.
At the write transistor TRW, one source/drain region is connected to a data line DTLn, and the gate electrode is connected to a scanning line SCLm. At the driving transistor TRD, one source/drain region is connected to the other source/drain region of the write transistor TRW, thereby configuring a first node ND1. One end of the capacitance unit C1 is connected to a power supply line PS1. At the capacitance unit C1, a predetermined reference voltage (later-described voltage VCC in the example shown in FIG. 26) is applied to one end, and the other end is connected to the gate electrode of the driving transistor TRD, thereby configuring a second node ND2. The scanning line SCLm is connected to an unshown scanning circuit, and the data line DTLn is connected to a signal output circuit 100.
At the first transistor TR1, one source/drain region is connected to the second node ND2, and the other source/drain region is connected to the other source/drain region of the driving transistor TRD. The first transistor TR1 makes up a switch circuit portion connected between the second node ND2 and the other source/drain region of the driving transistor TRD.
At the second transistor TR2, one source/drain region is connected to a power supply line PS3 to which is applied a predetermined initializing voltage VIni (e.g., −4 volts) for initialization of the potential of the second node ND2, and the other source/drain region is connected to the second node ND2. The second transistor TR2 makes TR1 makes up a switch circuit portion connected between the second node ND2 and the power supply line PS3 to which is applied the predetermined initializing voltage VIni.
At the third transistor TR3, one source/drain region is connected to a power supply line PS1 to which is applied a predetermined driving voltage VCC (e.g., 10 volts), and the other source/drain region is connected to the first node ND1. The third transistor TR3 makes up a switch circuit portion connected between the first node ND1 and the power supply line PS1 to which is applied the predetermined driving voltage VCC.
At the fourth transistor TR4, one source/drain region is connected to the other source/drain region of the driving transistor TRD, and the other source/drain region is connected to one end of a light emitting unit ELP (more specifically, the anode electrode of the light emitting unit ELP). The fourth transistor TR4 makes up a switch circuit portion connected between the other source/drain region of the driving transistor TRD and one end of the light emitting unit ELP.
The gate electrode of the write transistor TRW and the gate electrode of the first transistor TR1 are connected to the scanning line SCLm. The gate electrode of the second transistor TR2 is connected to an initialization control line AZm. Scanning signal supplied to an unshown scanning line SCLm-1 scanned immediately prior to the scanning line SCLm is also supplied to the initialization control line AZm. The gate electrodes of the third transistor TR3 and the fourth transistor TR4 are connected to a display control line CLm for controlling the lit/unlit state of the display element.
For example, each transistor is formed as a p-channel thin-film transistor (TFT), with the light emitting unit ELP provided on an interlayer-insulating later or the like, formed so as to cover the driving circuit. At the light emitting unit ELP, the anode electrode is connected to the other source/drain region of the fourth transistor TR4, and the cathode electrode is connected to a power supply line PS2. Voltage VCat (e.g., −10 volts) is applied to the cathode electrode of the light emitting unit ELP. Symbol CEL represents the capacitance of the light emitting unit ELP.
Now, when configuring transistors of TFTs, irregularity in threshold voltage is unavoidable to a certain extent. In the event that there is irregularity in the amount of current flowing through the light emitting unit ELP due to irregularity in the threshold value of the driving transistor TRD, the uniformity of luminance of the display device suffers. Accordingly, an arrangement has to be made where the amount of current flowing through the light emitting unit ELP is not affected by irregularity in the threshold value of the driving transistor TRD. As described later, the light emitting unit ELP is driven so as to be unaffected by irregularity in the threshold value of the driving transistor TRD.
A driving method of a display element at the m′th row and n′th column of a display device configured as a two-dimensional array of N×M display elements will be described with reference to FIGS. 27A and 27B. FIG. 27A illustrates a schematic timing chart of signals on the initialization control line AZm, scanning line SCLm, and display control line CLm. FIGS. 27B through 28B schematically illustrate the on/off states and the likes of the transistors of a 6Tr/1C driving circuit. To facilitate description, we will refer the period during which the initialization control line AZm is scanned as the “m−1′th horizontal scan period”, and the period during which the scanning line SCLm is scanned as the “m′th horizontal scan period”.
As shown in FIG. 27A, in the m−1′th horizontal scan period, an initialization process is carried out, which will be described in detail with reference to FIG. 27B. In the m−1′th horizontal scan period, the initialization control line AZm goes from a high level to a low level, and the display control line CLm goes from a low level to a high level. Note that the scanning line SCLm remains at the high level. Accordingly, during the m−1′th horizontal scan period, the write transistor TRW, first transistor TR1, third transistor TR3, and fourth transistor TR4 are in an off state, while the second transistor TR2 is in an on state.
A predetermined initialization voltage VIni for initializing the potential of the second node ND2 is applied to the second node ND2 via the second transistor TR2 which is in the on state. Accordingly, the potential of the second node ND2 is initialized.
Next, as shown in FIG. 27A, a video signal VSig is written in the m′th horizontal scanning period. At this time, threshold voltage canceling processing of the driving transistor TRD is performed in conjunction. Specifically, the second node ND2 and the other source/drain region of the driving transistor TRD are electrically connected, the video signal VSig is applied from the data line DTLn to the first node ND1 via the write transistor TRW which has been placed in an on state due to the signal from the scanning line SCLm, thereby changing the potential of the second node ND2 toward a potential which can be calculated by subtracting the threshold voltage Vth of the driving transistor TRD from the video signal VSig.
More detailed description will be made with reference to FIGS. 27A and 28A. In the m′th horizontal scanning period, the initialization control line AZm goes from a low level to a high level, and the scanning line SCLm goes from a high level to a low level. Note that the display control line CLm remains at the high level. Accordingly, at the m′th horizontal scanning period, the write transistor TRW and first transistor TR1 are in an on state, while the second transistor TR2, third transistor TR3, and fourth transistor TR4 are in an off state.
The second node ND2 and the other source/drain region of the driving transistor TRD are electrically connected via the first transistor TR1 which is in an on state, and the video signal VSig from the data line DTn is applied to the first node ND1 via the write transistor TRW which is in an on state due to the signal from the scanning line SCLm. Accordingly, the potential of the second node ND2 changes toward a voltage which can be calculated by subtracting the threshold voltage Vth of the driving transistor TRD from the video signal VSig.
According to the above-described initialization process, if the potential of the second node ND2 has been initialized such that the driving transistor TRD is in an on state at the start of the m′th horizontal scanning period, the potential of the second node ND2 changes toward the potential of the video signal VSig which is applied to the first node ND1. However, once the potential difference between the gate electrode of the driving transistor TRD and one source/drain region thereof reaches Vth, the driving transistor TRD goes to an off state. In this state, the potential of the second node ND2 is approximately (VSig−Vth).
Next, the light emitting unit ELP is driven by applying current to the light emitting unit ELP via the driving transistor TRD.
More detailed description will be made with reference to FIGS. 27A and 28B. At the end of the m′th horizontal scanning period, the scanning line SCLm goes from a low level to a high level. Also, the display control line CLm goes from a high level to a low level. Note that the initialization control line AZm remains at the high level. The third transistor TR3 and fourth transistor TR4 are in an on state, while the write transistor TRW, first transistor TR1, and second transistor TR2 are in an off state.
Driving voltage VCC is applied to one source/drain region of the driving transistor TRD via the third transistor TR3 which is in an on state. Also, the other source/drain region of the driving transistor TRD and one end of the light emitting unit ELP are connected via the fourth transistor TR4 which is in an on state.
The current flowing through the light emitting unit ELP is a drain current Ids which flows from the source region of the driving transistor TRD to the drain region thereof, so this can be expressed with the following expression (A) assuming that the driving transistor TRD operates ideally at the saturation region. As shown in FIG. 28B, the drain current Ids is applied to the light emitting unit ELP, and the light emitting unit ELP emits light at a luminance corresponding to the value of the drain current Ids.Ids=k·μ·(Vgs−Vth)2  (A)where μ represents effective mobility, L represents channel length, W represents channel width, Vgs represents voltage between the source region and gate region of the driving transistor TRD, and COX represents(relative permittivity of gate insulation layer)×(permittivity of vacuum)/(thickness of gate insulation layer)ink=(½)·(W/L)·COX.
Further, sinceVgs≈VCC−(VSig−Vth)  (B)holds, the above Expression (A) can be rewritten as follows.Ids=k·μ·(VCC−(VSig−Vth)−Vth)2=k·μ·(VCC−VSig)2  (C)
As can be clearly understood from the above Expression (C), the threshold voltage Vth of the driving transistor TRD has no bearing on the value of the drain current Ids. In other words, a drain current Ids corresponding to the video signal VSig can be applied to the light emitting unit ELP unaffected by the value of the threshold voltage Vth of the driving transistor TRD. With the above-described driving method, irregularities in the threshold voltage Vth of the driving transistor TRD do not affect the luminance of the display element.